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rev.1.2, apr.16.2004, page 1 of 28 m61140fp tuner single chip rej03f0023-0120z rev.1.2 apr.16.2004 description the m61140fp is a semiconductor integrated circuit consisting of tuner signal processing for ntsc color tv and vcrs. the circuit includes mixer circuit in tuning system, oscillator circuit, pll frequency synthesizer and vif/sif, which permits a smaller tuner system. features ? vif/sif inter carrier type for ntsc coil-less vco adjustment free aft high-speed if agc ? pll low phase noise and high-speed lock-up built-in band switch driver (4 port) i2c bus control available for both xo and external reference ? mixer/oscillator built-in u&v oscillator and mixer built-in if amplifier (unbalanced output) application tv, vcr recommended operating conditions supply voltage range --- 4.75 to 5.25v recommended supply voltage --- 5.0v
m61140fp rev.1.2, apr.16.2004, page 2 of 28 pin configuration and block diagram if2 gnd if out if2 vcc vif vcc cp vt drive logic vcc ref in logic gnd sda scl ads vif in 2 mo vcc vif in 1 rf agc out af bypass pfmst audio out pvhfl qif out pvhfh aft out mix filter 1 vif gnd mix filter 2 if agc 1 rf gnd apc filter v band in video out puhf vco f/b u band in 1 eq in u band in 2 video det out vreg rf agc delay if agc 2 eq f/b osc gnd v osc in 1 v osc out 1 v osc out 2 v osc in 2 u osc 1 u osc 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 band driver divider osc gnd rf gnd m/o vcc logic vcc logic gnd bus receiver xo if amp vreg coil-less vco if amp video det vif vcc lpf charge pump 15bit p.g divider psc 1/32, 1/33 v mix ref eq amp if agc det apc aft if2 gnd vif gnd rf agc qif amp lim amp fm det osc vhf uhf osc phase det u mix 18 19
m61140fp rev.1.2, apr.16.2004, page 3 of 28 absolute maximum ratings (ta=25oc, unless otherwise noted) parameter symbol ratings unit note supply voltage vcc 6 v mo block maximum allowable input vin 126 db v input voltage vimax 6 v pin25 to 27 port output voltage vo 6 v pin20 to 22,15 port output current (1) iopmax1 26 ma pin20, 21 port output current (2) iopmax2 7 ma pin15, 22 port output current (3) iopmax3 33 ma 2 circuits are on at same time pll block sda output current iosdamax 10 ma power consumption pd 750 mw recommended circuit board. when cu occupancy area is 50%. operating temperature topr -20 to +75 c storage temperature tstg -40 to +150 c temperature characteristics (maximum ratings) mounting in standard circuit board (70mmx70mmx1.6mmt epoxy board of one side copper ) ambient temperature ta (?c) 150 125 100 75 50 25 0 -20 allowable power consumption pd 250 500 750 1000 1250 1500 0 recommended operating condition (ta=25oc, unless otherwise noted) parameter symbol ratings unit note guarantee operating voltage vcc 4.5~5.3 v refer to data supply voltage range vcc 4.75~5.25 v operating frequency of crystal oscillator fopr 4.0 mhz port output current (1) ioprt1 0~25 ma pin 20,21 port output current (2) ioprt2 0~5 ma pin 15,22
m61140fp rev.1.2, apr.16.2004, page 4 of 28 pin description pin no. pin name function circuit diagram 1 video det out video detected output terminal. sif trap and sif b.p.f. are connected to this terminal. because of open emitter configuration, an externally connected drive resistor is necessary. 1 33 50 2 vreg regulated voltage output. approximately 3v output. 2 33 9.9k 6.2k 50 3 rf agc delay rf agc terminal. this terminal combine 4.5mhz sif signal input with set up the rf agc delay point. the rf agc delay point is set up by the dc component of input signal. ac component is fm detection threw the limiter amplifier. 3 33 5.1k 40 40p 43k 15p 4 if agc 2 if agc 2 terminal 44 if agc 1 if agc 2 terminal. external capacitor effects agc speed. when this terminal is grounded, the effect of vif amp gain becomes minimum. 44 4 33 50 10k 2.5k
m61140fp rev.1.2, apr.16.2004, page 5 of 28 pin no. pin name function circuit diagram 5 eq f/b equalizer feedback terminal. it is possible to change the frequency characteristic of the video signal by attaching l,c,r to this terminal. 33 2.2k 7k 5 500 6 osc gnd osc ground terminal. 7 v osc in 1 8 v osc out 1 9 v osc out 2 10 v osc in 2 vhf oscillator circuit is connected externally. when band byte bit puhf is set "1", bias current of oscillator transistor turns off. 10 9 24 8 7 400 400 2.2k 2.2k 600 600 11 u osc 1 12 u osc 2 uhf oscillator circuit is connected externally. when band byte bit puhf is set "1", bias current of oscillator transistor turns on. 36 11 12 36 11 12 400 400 3p 3p 2.5p 2.5p 13 u band in 1 14 u band in 2 uhf rf input terminal. input type is balance input. in the case of unbalance input, grounding of either pin 13 or 14 with capacitor is required, while input to the other pin. 24 14 13 1.8k 1.8k
m61140fp rev.1.2, apr.16.2004, page 6 of 28 pin no. pin name function circuit diagram 15 puhf band change drive terminal. output configuration is pnp open collector. when band selection bit puhf is set "1", current is output. 24 47k 15 16 v band in vhf rf input terminal. input type is unbalance. 24 16 2.2k 2.2k 17 rf gnd rf (mixer) gnd terminal. 18 mix filter 1 19 mix filter 2 mixer output terminal. the output terminal is open collector type, single-tuned filter is connected. this pin is pull-up through power supply in order for voltage to be above 4.2v. 24 18 19 200 20p 200 20p 4k 4k 20 pvhfh 21 pvhfl band change drive terminal. output configuration is pnp open collector. when band selection bit pvhfl or pvhfh is set "1", current is output. 28 47k 20 21
m61140fp rev.1.2, apr.16.2004, page 7 of 28 pin no. pin name function circuit diagram 22 pfmst band change drive terminal. output configuration is pnp open collector. when band selection bit pfmst is set "1", current is output. reference frequency or divided frequency of local are output by test mode condition. 28 47k 22 23 rf agc out rf agc output terminal. it is current drive type. 23 33 50 24 24 mo vcc mixer and oscillator block power supply. 25 ads address setting input terminal. address bit "ma1","ma2" is selected by the potential at this terminal. 25 28 25 28 40k 13k 1k 26 scl scl input terminal. 28 26 1k
m61140fp rev.1.2, apr.16.2004, page 8 of 28 pin no. pin name function circuit diagram 27 sda sda input terminal. reading and writing of data confirm to i 2 c bus of philips. 28 27 1k ack 28 logic vcc logic block power supply. 29 ref in reference frequency input terminal. connect crystal oscillator at this terminal, or external signal (sine wave).in this case of using external sine wave signal, pull down this terminal with 1.5k to 3.3k ? . 28 29 1.3k 500 1.3k 500 30 logic gnd logic block power supply. 31 vt drive filter transistor drive terminal. as for drive output, control bit "os" controls it on or off 32 cp charge pump output terminal. when the phase of the divide frequency of local is lead compared with the reference frequency, the "source" current state becomes active. if it is lag, the "sink" current becomes active. if the phase are the same, the high impedance state becomes active. 32 31 28 d u os 150 1k 50 33 vif vcc vif block power supply. 34 if2 vcc power supply terminal exclusively for if amp output (pin 34) circuit. 35 if out if amp output terminal. this terminal is a low impedance and output if frequency. 34 35 20 36 if2 gnd if2 grand terminal. this grand is exclusively used by circuit of if amplifier
m61140fp rev.1.2, apr.16.2004, page 9 of 28 pin no. pin name function circuit diagram 37 vif in 1 38 vif in 2 if signal thew saw filter is input. it is a balance type input. 37 33 2k 38 2k 14k 39 af bypass af bypass terminal. it is connected to one of the input of a differential amplifier, external capacitor provides ac filtering. when resistor is connected in series with capacitor, it is possible to lows the amplitude of the audio output. when audio output terminal is not used, please connect pin 22 to gnd. 37 33 2k 38 2k 14k 40 audio out sound output terminal. de- emphasis is achieved by external components. 40 33 200 41 qif out qif output terminal. fm signal which is converted to 4.5mhz is output. additionally, this pin has dual function of being vif vco type selection. connected to gnd via 1.2k ? 41 33 400 30k 6p
m61140fp rev.1.2, apr.16.2004, page 10 of 28 pin no. pin name function circuit diagram 42 aft out aft output terminal. because of pulse-like signal output, a smoothing capacitor is connected externally. in addition, aft detection sensitivity is set by external resistor. 42 33 50 300u 300u 43 vif gnd vif gnd terminal. 45 apc filter apc filter terminal. it is the loop filter terminal which a vif signal is made to lock vco and keeps frequency constant. 17 28 21 k 21 k 300 300 45 33 46 video out video output terminal. the signal inputted into the eqi terminal is outputted. 33 46 200 47 vco f/b vco feedback terminal. the feedback is to keep the free- running frequency of the built-in vco. 47 33 10k 20k
m61140fp rev.1.2, apr.16.2004, page 11 of 28 pin no. pin name function circuit diagram 48 eq in the video signal threw the sif trap is input to this terminal. dc impression from pin 1 is required for the input to 48 pins. 33 48 100 setting data m61140fp's bus format is based on philips's i 2 c-bus. bidirectional bus communication control can be performed. it consists of write mode which receives various data, and read mode which transmits data. recognition in write mode and read mode is performed by specification of the last bit on address byte (r/w bit). when the setup of a r/w bit is "0", it is set as write mode and, in the case of "1", is set as read mode. furthermore, it has the address in which four programs are possible. it enables this to use two or more devices on the same i 2 c bus. moreover, four programmable addresses are possible. therefore, two or more devices become usable on i 2 c bus. a setup of an address is chosen by the voltage impressed to an address setting terminal (ads:25 pin). if the address byte in agreement is received, a data line will be set to "l" between knowledge, and at the time of write mode, if data byte is received, sda line between knowledge will be set to "l." it shows a definition of bus protocol admitted in the following. mode_1 sta ca db1 db2 cb1 cb2 sto mode_2 sta ca cb1 cb2 db1 db2 sto mode_3 sta ca db1 db2 sto mode_4 sta ca cb1 cb2 sto sta : start condition sto : stop condition ca : chip address db1 : divider data byte 1 db2 : divider data byte 2 cb1 : control data byte 1 cb2 : band data byte 2
m61140fp rev.1.2, apr.16.2004, page 12 of 28 (1) write mode the information of 5 bytes required for circuit operational chip address, control data and band sw data of 2 bytes and divider data of 2 bytes. after the chip address input, 2 or 4 bytes can be received. function bit is contained in the first and the third data byte to distinguish between divider and 'control data/band sw data', with "0" going ahead of divider data, and "1" going ahead of 'control data/band swdata'. the timing of writing data for bus protocol mode is shown in the figure below. divider data uses 15 bits and is read in at the rise of the eighth clock bit of the second byte divider data (db2). control data (cb1) and band sw-data (bb) are each read in at the rise of their eighth clock bit. timing chart read into latch read into latch read into latch address db1 db2 cb1 cb2 sda scl write mode data format byte msb lsb address byte (ca) 1 1 0 0 0 ma1 ma0 r/w=0 a divider byte1 (db1) 0 n14 n13 n12 n11 n10 n9 n8 a divider byte2 (db2) n7 n6 n5 n4 n3 n2 n1 n0 a control byte (cb1) 1 cp t2 t1 t0 rsa rsb os a band byte (cb2) x x x x puhf pfmst pvhfh pvhfl a programmable address bit address input voltage applied to ads [v] ma1 ma0 0 to 0.1xvcc 0 0 open or 0.2 to 0.3xvcc 0 1 0.4xvcc to 0.6xvcc 1 0 0.9xvcc to vcc 1 1 n14 to n0 : set up for division ratio of the programmable divider frequency of vco fvco: fvco=fref x n division ratio n: n=n14(2^14 )+n13(2^13 )+ --- +n0(2^0) range of division ratio n: n=1,024 to 32,767 fref: reference frequency of phase comparator cp: set up the charge pump current cp charge pump current * 0 70 a 1 300 a note: * current of charge pump is typ current in the case of setting current 270 a,when pll is locked, charge pump current is automatically switched to cp=o (70 a).
m61140fp rev.1.2, apr.16.2004, page 13 of 28 t2, t1, t0 : set up for test mode cp t2 t1 t0 charge pump test output test sw mode 0 0 0 x cp switched off - off normal mode 1 0 0 x cp switched on - off normal mode x 0 1 x high impedance - off test mode x 1 1 0 sink - off test mode x 1 1 1 source - off test mode 0 1 0 0 high impedance fref off test mode 1 1 0 x cp switched on - on tv test mode 0 1 0 1 high impedance f1/n off test mode note : fref and f1/n is available on pin pfmst(pin 22). test sw is for the mix filter damping switch rsa : set up tuning step rsa rsb division ratio tuning step frequency @4mhz x'tal 0 1 1/128 31.25khz 1 1 1/64 62.5khz x 0 1/80 50.0khz os : set up drive output os drive output mode 0 on normal mode 1 off("l")level test mode pfmst, puhf , pvhfl,pvhfh : port setting pfmst,puhf,pvhfl,pvhfh output 0 off 1 on pnp open collector output. when puhf is "off", mixer and oscillator active vhf mode. (2) read mode data format at the time of read mode, a power-on reset state, a phase comparison machine lock detector output state, and the state of the charge pump current change sw are outputted to a master device. read mode data format byte msb lsb address byte 1 1 0 0 0 ma1 ma0 r/w=1 a status byte por fl acps x x x x x a x: 0 or 1 don't care por: power on reset flag. output is "1" at power-on set to "1" when the time of a power supply voltage injection or power supply voltage falls in about 3v or less. reset by "0", if a request to send is carried out in read mode and a flag is returned. power supply voltage is about 3v or more, reset by "0", after returning a flag in read mode. fl: lock detector flag. output is "1" at locked, output is "0" at unlocked. acps: automatic charge pump current flag. output is "0" at charge pump current automatically switched mode, output is "1" at other mode.
m61140fp rev.1.2, apr.16.2004, page 14 of 28 (3) power on reset the initial status is shown as below when supply voltage is turned on. if supply voltage becomes less than about 3.0v, the initial status is set. byte msb lsb divider byte1 (db1) 0 x x x x x x x divider byte2 (db2) x x x x x x x x control byte (cb1) 1 1 0 1 x 1 1 1 band byte (cb2) x x x x 0 0 0 0 (4) data format example ex1.us-tv-ch2 (frf=55.25mhz,fosc=101mhz),cp sw=on, reference frequency=4mhz,31.25khzstep, puhf="on" byte msb lsb address byte 1 1 0 0 0 ma1 ma0 r/w=0 a divider byte1 (db1) 0 0 0 0 1 1 0 0 a divider byte2 (db2) 1 0 1 0 0 0 0 0 a control byte (cb1) 1 1 0 0 0 0 1 0 a band byte (cb2) x x x x 0 0 0 1 a divide ratio n =101 * 10 6 /31.25 * 10 3 = 3232 = 2 11 +2 10 +2 7 +2 5 purchase of renesas technology electric corporation's i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips
m61140fp rev.1.2, apr.16.2004, page 15 of 28 electrical characteristics dc characteristics (ta=25c, vcc=5.0v otherwise noted.) limits item symbol measure point input sg condition switches set to position "1" unless otherwise noted min typ max unit note if vcc current iccif 33 - sw33=2 40 53 66 ma if2 vcc current iccif2 34 - sw34=2 14 19 24 ma m/o vcc current iccrf 24 - sw24=2 14 18 23 ma logic vcc current(1) icclo1 28 - sw28=2 port off 11 14 18 ma logic vcc current(2) icclo2 28 - sw28=2, io(pvhfl) or io(pvhfh)=20ma 27 37 46 ma logic vcc current(3) icclo3 28 - sw28=2, io(pfmst) or io(puhf)=5ma 15 20 25 ma
m61140fp rev.1.2, apr.16.2004, page 16 of 28 mixer and osc block (ta=25c, vcc=5.0v otherwise noted.) limits item symbol measure point input sg condition switches set to position "1" unless otherwise noted min typ max unit note conversion gain1 gvcv1 35,16 - frf=55.25mhz, cw 20 23 26 db conversion gain2 gvcv2 35,16 - frf=361.25mhz, cw 20 23 26 db nf1 nfv1 35 - frf=55.25mhz, cw - 16.5 18 db nf2 nfv2 35 - frf=361.25mhz, cw - 17.5 20 db cross modulation1 cmv1 35 - fd=55.25mhz, cw fud=fd6mhz, am100khz, 30% -28 -25 - dbm cross modulation2 cmv2 35 - fd=361.25mhz, cw fud=fd6mhz, am100khz, 30% -28 -25 - dbm cs beat1 cs1 35 - fp=241.25mhz, fs=245.75mhz fc=244.83mhz, am100khz, 30% 55 60 - dbc v h f cs beat1 cs2 35 - fp=241.25mhz, fs=245.75mhz fc=244.83mhz, am100khz,30% 55 60 - dbc conversion gain3 gvcu3 35 - frf=367.25mhz, cw 27 30 33 db conversion gain4 gvcu4 35 - frf=801.25mhz, cw 27 30 33 db nf1 nfu1 35 - frf=367.25mhz, cw - 11.5 13 db nf2 nfu2 35 - frf=801.25mhz, cw - 13 15 db cross modulation1(-) cmu1(-) 35 - fd=367.25mhz, cw fud=fd-6mhz, am100khz, 30% -31 -28 - dbm cross modulation1(+) cmu1(+) 35 - fd=367.25mhz, cw fud=fd+6mhz, am100khz, 30% -37 -34 - dbm cross modulation2(-) cmu2(-) 35 - fd=801.25mhz, cw fud=fd-6mhz, am100khz, 30% -31 -28 - dbm cross modulation2(+) cmu2(+) 35 - fd=801.25mhz, cw fud=fd+6mhz, am100khz, 30% -37 -34 - dbm u h f cs beat3 cs3 35 - fp=615.25mhz, fs=627.75mhz fc=618.83mhz, voif=-10dbm 55 60 - dbc
m61140fp rev.1.2, apr.16.2004, page 17 of 28 mixer and osc block (ta=25c,vcc=5.0v otherwise noted.) limits item symbol measure point input sg condition switches set to position "1" unless otherwise noted min typ max unit note 6ch beat int6ch 35 - fp=83.25mhz, fs=87.75mhz voif=-10dbm 55 60 - dbc a5ch beat inta5ch 35 - fp=91.25mhz, voif=-10dbm 60 65 - dbc 5ch beat int5ch 35 - fp1=83.25mhz, fp=77.25mhz voif=-10dbm 60 65 - dbc psc beat1 psc183 35 - fosc=183mhz - - -85 dbm psc beat2 psc366 35 - fosc=366mhz - - -85 dbm b e a t psc beat3 psc732 35 - fosc=732mhz - - -85 dbm vhf osc power supply shift ? fosc_v 35 - ? vcc=10% - - 500 khz vhf osc swon drift ? foscv_t 35 - vccon 3sec to 5min - - 500 khz vhf osc c/n1 c/n(v1) 35 - fp=83.25mhz, voif=-10dbm +/-50khz offset 65 - - dbc vhf osc c/n2 c/n(v2) 35 - fp=241.25mhz, voif=-10dbm +/-50khz offset 65 - - dbc uhf osc power supply shift ? fosc_u 35 - ? vcc =10% - - 500 khz uhf osc swon drift ? foscu_t 35 - vccon 3sec to 5min 55 - - khz o s c uhf osc c/n c/n(u) 35 - fp=615.25mhz, voif=-10dbm +/-50khz offset 65 - - dbc
m61140fp rev.1.2, apr.16.2004, page 18 of 28 pll block (ta=25c,vcc=5.0v otherwise noted.) limits item symbol measure point input sg condition switches set to position "1" unless otherwise noted min typ max unit note high input voltage vih 26,27 - sw26,27=2 2.3 - vcc v low input voltage vil 26,27 - sw26,27=2 - - 1.0 v high input current iih 26,27 - sw25a,26,27=2 vi=4.0v - - 10 a s d a / s c l low input current iil 26,27 - sw25a,26,27=2 vi=0.4v - -1 -10 a low output voltage vosl 27 - sw25a,27=2 io=3ma - - 0.4 v s d a leakage current ioslk 27 - sw25a,27=2 vo=5.0v - - 10 a high input current viah 25 - sw25,25a=2 vi=5.0v - - 600 a a d s low input current iial 25 - sw25,25a=2 vi=0.4v - - -200 a output voltage1 vop1 20,21 - sw20,21=2 io=-25ma 4.6 4.8 - v output voltage2 vop2 15,22 - sw15,22=2 io=-5ma 4.6 4.8 - v p o r t leakage current ioplk 15 20~22 - sw15,20,21,22=2 output "off" - - 10 a high output current icph 32 - sw32=2 vo=2.5v 170 300 400 a low output current icpl 32 - sw32=2 vo=2.5v 55 75 115 a c p leakage current icplk 32 - sw32=2 vo=2.5v,output "off" - - 50 na v t tuning drive output iovt 31 - sw31=2 vo=0.5v - - 2.0 ma operational frequency of crystal osc fxin 29 - 3.2 4.0 4.4 mhz absolute value rxin 29 - 2.0 - - k ? x i n sensitivity of external signal vixin 29,22 sg17 sw29=2,sine wave signal input data(t2,t1,t0)="01x" 50 - 600 mvp -p * 14
m61140fp rev.1.2, apr.16.2004, page 19 of 28 data input block (ta=25c,vcc=5.0v otherwise noted.) limits item symbol measure point input sg condition switches set to position "1" unless otherwise noted min typ max unit note clock frequency fscl 26 0 100 400 khz bus free time tbuf 27 1.3 - - sec data hold time thdsta 27 0.6 - - sec scl low hold time tlow 26 1.3 - - sec scl high hold time thigh 26 0.6 - - sec set up time tsusta 26,27 0.6 - - sec data hold time thddat 26,27 0 - - sec data set up time tsudat 26,27 100 - - nsec rise time tr 26,27 - - 300 nsec fall time tf 26,27 - - 300 nsec set up time tsusto 26 0.6 - - sec timing chart sda scl tbu tlow tr thdsta thddat thigh tsudat tsusta tsusto tf thdsta [stop] condition [start] condition [start] condition [stop] condition
m61140fp rev.1.2, apr.16.2004, page 20 of 28 vif block1 (ta=25c, vcc=5.0v otherwise noted.) limits item symbol measure point input sg condition switches set to position "1" unless otherwise noted min typ max unit note video output level vodet 46 sg1 0.85 1.15 1.35 vp-p sync tip voltage vosnk 46 sg2 1.1 1.3 1.5 v video s/n videos/ n 46 sg2 5mhz lpf 48 50 - db * 1 video out freq. response bw 1 sg3 6 7 - mhz * 2 input sensitivity vinmin 1,37,38 sg4 vo=-3db point - 45 52 db v * 3 max. if input vinmax 1,37,38 sg5 vo=-3db point 101 105 - db v * 4 agc range gr - gr = vinmax - vin min 52 60 - db * 5 capture range u cr-u 46,37,38 sg9 0.6 0.8 - mhz * 6 capture range l cr-l 46,37,38 sg9 1.1 1.5 - mhz * 7 inter modulation im 1 sg11 32 40 - db * 8 d/g dg 1 sg12 - 3 5 % d/p dp 1 sg12 - 3 5 deg input impedance zin 37,38 - dc - 2k - ? input capacitance yin 37,38 - 40mhz - 5 - pf rf agc max voltage v23h 23 sg6 4 4.3 4.6 v rf agc min voltage v23l 23 sg7 0 0.3 0.6 v rfagc delay point vi23 23,37,38 sg8 @3pin open 82 85 88 db v * 9 vif block2 (ta=25c,vcc=5.0v otherwise noted.) limits item symbol measure point input sg condition switches set to position "1" unless otherwise noted min typ max unit note freerun frequency fvco 42 sg17 sw42,29=2,44pin "gnd" data (t2,t1,t0="01x") -500 - 500 khz * 15 aft sensitivity 42 sg10 @360k/360k 0.1 f 12 24 36 mv/ khz * 10 aft high output voltage v42h 42 sg10 4.3 4.7 5 v aft low output voltage v42l 42 sg10 0 0.3 0.7 v aft center voltage v42c1 42 sg18 frequency=58.75mhz 2.4 2.5 2.6 v aft center voltage v42c2 42 sg2 frequency=45.75mhz 2.4 2.5 2.6 v
m61140fp rev.1.2, apr.16.2004, page 21 of 28 sif block (ta=25c,vcc=5.0v otherwise noted.) limits item symbol measure point input sg condition switches set to position "1" unless otherwise noted min typ max unit note audio out level voaf 40 sg13 sw3=2 @pin39:0.22 f 500 770 1040 mvrms audio out thd thdaf 40 sg13 sw3=2 @pin39:0.22 f - 0.4 0.9 % af s/n af s/n 40 sg16 sw3=2 @pin39:0.22 f 51 56 - db * 11 limiting sensitivity lim 3,40 sg14 sw3=2 s/n=30db point - 50 55 db v * 12 amr amr 40 sg15 sw3=2 44 50 - db * 13 qif output voqif 41 sg16 sw3=2 86 92 - db v measurement diagram 10 n 0. 01u 47u 0. 01u tp35 12 360k 360k 0. 1u 1n 0. 01u 7.5k 0. 22 0. 1u 0. 01u 0. 1u 27p 27p 50 tp23 v ba nd in u band in v46a tp42 tp41 2200p 5. 6k 100k 2200p 1k 2. 7k 0. 01u 0. 022u 22 u 56p 240 330 15 u 0. 1u 5v 0. 01u 0. 01u 1 2 1 v 1 2 0. 01u 1 2 1 2 tp4 tp1 1 2 lp f v46b tp40 vif in 2 5v a 12 5v a 10p 5v a 5v a 12 12 12 12 1 2 a 12 1 2 v a 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15bit p. g d i v i d e r ps c 1/32, 1/33 v mix u mix ph a s e det b and driver re f divider os c gn d rf g nd m/o vcc log ic v c c log ic g n d bu s receiver xo if amp eq amp vr eg if a g c de t coil-les s vc o apc aft if a mp video det vi f vc c if 2 gn d lp f rf ag c qi f amp li m amp fm det char ge pump os c vhf os c uh f 47p 0. 22 200 1000p vi f g n d 1 2 10k 22k 50 50 0 6800p 7. 5k vt 10 k 68 100k 27k 100k 27k if 2 v cc 1n 1n sw 34 sw 32 sw 31 sw 33 sw 28 sw 27 sw 26 sw 25 s w25a sw 22 sw 24 sw 21 10k sw 22 sw 15 sw 42 sw 44 sw 46 sw 3 1 2 sw 29 2 1 10p 0. 5p 5p 5p 5p 5p 56p 2p 2200p 2200p 1n 1n 1n 1n 1n 1n 10 n 0. 01 47 0. 01 tp35 12 360k 360k 0. 1 1n 0. 01 7.5k 0. 0. 1 0. 01 0. 1 27p 27p 50 tp23 v ba nd in u band in v46a tp42 tp41 2200p 5. 6k 100k 2200p 1k 2. 7k 0. 01 0. 022 22 56p 240 330 15 0. 1 5v 0. 01 0. 01 1 2 1 v 1 2 0. 01 1 2 1 2 tp4 tp1 1 2 lp f v46b tp40 vif in 2 5v a 12 12 5v a 10p 5v a 5v a 12 12 12 12 12 12 12 12 1 2 a a 12 12 1 2 v v a a 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15bit p. g d i v i d e r ps c 1/32, 1/33 v mix u mix ph a s e det b and driver re f divider os c gn d rf g nd m/o vcc log ic v c c log ic g n d bu s receiver xo if amp eq amp vr eg if a g c de t coil-les s vc o apc aft if a mp video det vi f vc c if 2 gn d lp f rf ag c qi f amp li m amp fm det char ge pump os c vhf os c uh f 47p 0. 22 200 1000p vi f g n d 1 2 1 2 10k 22k 50 50 0 6800p 7. 5k vt 10 k 68 100k 27k 100k 27k if 2 v cc 1n 1n sw 34 sw 32 sw 31 sw 33 sw 28 sw 27 sw 26 sw 25 s w25a sw 22 sw 24 sw 21 10k sw 22 sw 15 sw 42 sw 44 sw 46 sw 3 1 2 sw 29 2 1 10p 0. 5p 5p 5p 5p 5p 56p 2p 2200p 2200p 1n 1n 1n 1n 1n 1n 10p 4mhz 10p 4mhz 0.1u 0.01u 33v 2200p 18k 100p 22k vt 0.1 0.01 33v 2200p 18k 100p 22k vt i 2 c bus 2.2k
m61140fp rev.1.2, apr.16.2004, page 22 of 28 input signal sg 50ohm termination 1 f0=45.75mhz vi=90db v fm=20khz am=77.8% 2 f0=45.75mhz vi=90db v cw 3 f1=45.75mhz f2=frequency variable vi=90db v vi=70db v cw cw mixed signal 4 f0=45.75mhz level variable fm=20khz am=77.8% 5 f0=45.75mhz level variable fm=20khz am=14.0% 6 f0=45.75mhz vi=80db v cw 7 f0=45.75mhz vi=110db v cw 8 f0=45.75mhz level variable cw 9 f0=frequency variable vi=90db v fm=20khz am=77.8% 10 f0=frequency variable vi=90db v cw 11 f1=45.75mhz f2=42.17mhz f3=41.25mhz vi=90db v vi=80db v vi=80db v cw cw cw mixed signal 12 f0=45.75mhz sync tip level 90db 10 stair-steps waveform tv moduration=87.5% 13 f0=4.5mhz vi=90db v fm=1khz +/- 25khz dev 14 f0=4.5mhz level variable fm=1khz +/- 25khz dev 15 f0=4.5mhz vi=90db v fm=1khz am=30% 16 f0=4.5mhz vi=90db v cw 17 f0=4.0mhz level variable cw 18 f0=58.75mhz vi=90db v cw
m61140fp rev.1.2, apr.16.2004, page 23 of 28 measurement of electrical characteristic notes 1. video s/n input sg2 to vif in and measure the video out (pin 46) noise in r.m.s. at tp46b through a 5mhz (-3db) l.p.f. 0.7xvodet noise s/n=20lo g ( db ) 2. video band width 1. measure the 1mhz component level of video output tp1 with a spectrum analyzer when sg3 (f2=44.75mhz) is input to vif in. at that time, measure the voltage at tp44 with sw8, set to position 2, and then fix v8 at that voltage. 2. reduce f2and measure the value of (f2-f1) when the (f2-f1) component level reaches -3db from the 1mhz component level as shown below. video det out 1mhz bw -3db ( f2-f1 ) 3. input sensitivity input sg4 (vi=90db ) to vif in , and then gradually reduce vi and measure the input level when the 20khz component of video output tp46a reaches -3db from vo det level. 4. maximum allowable input 1. input sg5 (vi=90db ) to vif in, and measure the level of the 20khz component of video output. 2. gradually increase the vi of sg and measure the input level when the output reaches -3db. 5. agc control range gr=vinmax-vinmin (db) 6. capture range u 1. increase the frequency of sg9 until the vco is out of locked-oscillation 2. and decrease the frequency of sg9 and measure the frequency fu when the vco is locked. cr-u=fu-45.75 (mhz) 7. capture range l 1. decrease the frequency of sg9 until the vco is out of locked-oscillation. 2. and increase the frequency of sg9 and measure the frequency fl when the vco is locked. cr-l=45.75-fl (mhz) 8. inter modulation 1. input sg11 to vif in, and measure video output tp9 with an oscilloscope. 2. adjust agc filter voltage v44 so that the minimum dc level of the output waveform is 1.5v. 3. at that time, measure tp1 with a spectrum analyzer the inter modulation is defined as a difference between 0.92mhz and3.58 mhz frequency components. 9. rf agc operating voltage: input sg8 to vif in and gradually reduce vi and then measure the input level when rf agc output reaches 1/2vcc, as shown below. v23 1/2vcc v23h vi v23l
m61140fp rev.1.2, apr.16.2004, page 24 of 28 10. aft sensitivity, maximum aft voltage, minimum aft voltage 1. input sg10 to vif in, and set the frequency of sg10 so that the voltage of aft output tp42 is 3(v). this frequency is named f(3). 2. set the frequency of sg10 so that the aft output voltage is 2(v). this frequency is named f(2). 3. in the graph shown below, maximum and minimum dc voltage are v42h and v42l, respectively. 1000mv f(2)-f(3) (khz) v42 3v 2v f ( 3 ) f ( 2 ) v42h v42l = ( mv/khz ) 11. af s/n 1. input sg19 to lim in, and measure the output noise level of audio output (tp40). this level is named vn. voaf vn s/n=20lo g (db) 12. limiting sensitivity 1. input sg14 to lim in, and measure the 1khz component level of af output tp40. 2. input sg17 to lim in, and measure the noise level of af output tp40 . 3. the input limiting sensitivity is defined as the input level when the difference between each 1khz components of audio output (tp40) is 30db, as shown below. af 30db audio output while sg14 is input. audio output while sg17 is input. 13. am rejection 1. input sg15 to lim in, and measure the output level of audio output (tp40). this level is named vam. 2. amr is vo af (mvrms) (mvrms) vam amr=20log (db) 14. xin sensitivity of external signal 1. input data that control byte data cp,t2,t1,t0 is "0100" and rsa,rsa is"01" 2. the reference frequency is output to pin 22, measure the frequency with counter. 3. input sensitivity is defined as the input level when the frequency is less than plus-or-minus 1ppm of 31.25khz. 15. freerun frequency 1. input data that control byte data cp,t2,t1,t0 is "01x". 2. the reference frequency is output to pin 42, measure the frequency with counter. this frequency is named fmoni. freerun frequency (fous) is 52.9524[mhz] - fmoni x 9 [mhz] freerun frequency (fojp) is 65.9512[mhz] - fmoni x 9 [mhz]
m61140fp rev.1.2, apr.16.2004, page 25 of 28 application board example
m61140fp rev.1.2, apr.16.2004, page 26 of 28 application example ch a r ge pump sa w sa w 47p 0.22 200 1000p 360k 360k 0.1 1.5k for j ap an mode 0.01 0.01 7.5k 0.22 1n 5v 0.01 0.1 10 p 0.01 5v 0.01 5v 1n to mo d re f i n ( 4 mhz ) sd a s cl a ds 0.1 27p 27p 50 rf a g c o u t pf ms t pv h f l pv h f h v ba nd in u ban d in pu h f v ideo out aft out qi f o ut a udio ou t 2200p 5.6k 100k 2200p 1k 0.01 2.7k 33 v 0.1 2200p 18k 100p 22k 0.01 0.1 0.022 22 56p 240 330 15 0.1 rf a g c delay 27k 5v 47 vt 1n 1n 0.01 5v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15 bit p.g d ivider ps c 1/32, 1/33 v mix u mix ph a s e det b and driver re f divider os c gn d rf gnd m/o vcc log ic v c c log ic g n d bu s receiver xo if amp eq amp vr eg if a g c det co il- le s s vc o apc aft if a mp v ideo det vi f v cc if 2 g n d vi f g n d lp f rf ag c qi f amp li m amp fm det ch a r ge pump os c vhf uh f os c 46 6800p 7.5k vt 10k 68 5p 5p 5p 5p 56p 2p 2200p 2200p 100k 27k 1n 10p 0.5p 100k 1n 1n 0.01 0.01 0.01 27k *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 *14 *15 *16 *17 *18 *19 *7 *20 *21 2.2k
m61140fp rev.1.2, apr.16.2004, page 27 of 28 application note *1 2sc2735 equivalent made by renesas *2 45.75mhz saw filter made by epcos *3 4.5mhz trap made by murata *4 4.5mhz b.p.f. made by murata *5 hc-49/u equivalent made by daishinku. load capacitance= 20pf,motinal resistance: less 300 ? *6,7 hvc306b equivalent made by renesas *8 ma2s77 equivalent made by matsushita *9 0.1mm 3mm 6t x2 p886ans-0194vn made by toko *10 0.5mm 2.4mm 2.5t *11 0.5mm 2.4mm 2.5t *12 0.5mm 2.4mm 8.5t *13,14 the bypass capacitor of vcc is arranged near the logicgnd pin. *15 in order to mitigate the surroundings lump by the vif input, the balanced connection from a saw filter to the vif input pin of 37.38 recommends a putter which serves as a 1t coil by tip c or the jumper. *16-19 in order to stop digital beat which goes via the port output from logic vcc, bypass capacitor arranged near the port output pin. *21 it is high impedance. keep away from videodetout and eq f/b pin. notes about the handling of ic *20 the direct power supply impression to vt terminal is forbidden. when power supply impression is required, please impress through the resistance for current restrictions. depending on the case, it is drive current from 31 pin, and excessive collector current flows and breaks to an external transistor. because there is a possibility of also destroying ic by the destruction. * since this ic is using the detailed process, be careful of serge enough. especially careful 1,7,8,9,10,25,26,27,32,48 pins.
m61140fp rev.1.2, apr.16.2004, page 28 of 28 package dimensions lqfp48-p-77-0.50 ? weight(g) ? jedec code eiaj package code lead mater ial c u allo y 48p6q-a plastic 48pin 7 ? 7mm bod y lqfp ? 0.1 ? ? 0.2 ? ? ? ? ? ? ? ? ? symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimens ion in millimeters h d a 1 0.225 ? ? i 2 1.0 ? ? m d 7.4 ? ? m e 7.4 8? 0? 0.1 1.0 0. 65 0.5 0.35 9.2 9.0 8.8 9.2 9.0 8.8 0.5 7.1 7.0 6.9 7.1 7.0 6.9 0.175 0.125 0.105 0.27 0.22 0.17 1.4 0 1.7 e e e h e 1 48 37 24 25 36 12 13 h d d m d m e a f y b 2 i 2 r ecommended mount p a d a 1 a 2 l 1 l detail f lp a3 c lp 0.45 0.6 0.25 0.75 0.08 x a3 e b x m mmp
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 2004. renesas tec hnology corp., all rights reserved. printed in japan. colophon .1.0

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